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at28c256 256k (32k x 8) paged cmos e 2 prom features fast read access time - 150 ns automatic page write operation internal address and data latches for 64-bytes internal control timer fast write cycle times page write cycle time: 3 ms or 10 ms maximum 1 to 64-byte page write operation low power dissipation 50 ma active current 200 m a cmos standby current hardware and software data protection data polling for end of write detection high reliability cmos technology endurance: 10 4 or 10 5 cycles data retention: 10 years single 5v 10% supply cmos and ttl compatible inputs and outputs jedec approved byte-wide pinout full military, commercial, and industrial temperature ranges description the at28c256 is a high-performance electrically erasable and programmable read only memory. its 256k of memory is organized as 32,768 words by 8 bits. manufac- tured with atmels advanced nonvolatile cmos technology, the device offers access times to 150 ns with power dissipation of just 440 mw. when the device is deselected, the cmos standby current is less than 200 m a. (continued) lcc, plcc top view pin name function a0 - a14 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc dont connect pin configurations tsop top view pga top view note: plcc package pins 1 and 17 are dont connect. cerdip, pdip, flatpack, soic top view 0006f at28c256 2-217
block diagram the at28c256 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 64-byte page register to allow writ- ing of up to 64-bytes simultaneously. during a write cycle, the addresses and 1 to 64-bytes of data are internally latched, freeing the address and data bus for other opera- tions. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmels 28c256 has additional features to ensure high quality and manufacturability. the device utilizes internal error correction for extended endurance and improved data retention characteristics. an optional software data protection mechanism is available to guard against inad- vertent writes. the device also includes an extra 64-bytes of e 2 prom for device identification or tracking. description (continued) temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* 2-218 at28c256
device operation read: the at28c256 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention in their system. byte write: a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cy- cle. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. once a byte write has been started it will automatically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectively be a poll- ing operation. page write: the page write operation of the at28c256 allows 1 to 64-bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 addi- tional bytes. each successive byte must be written within 150 m s (t blc ) of the previous byte. if the t blc limit is ex- ceeded the at28c256 will cease accepting data and com- mence the internal programming operation. all bytes dur- ing a page write operation must reside on the same page as defined by the state of the a6 - a14 inputs. for each we high to low transition during the page write operation, a6 - a14 must be the same. the a0 to a5 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. data polling: the at28c256 features data polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. toggle bit: in addition to data polling the at28c256 provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling be- tween one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. (continued) data protection: if precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. hardware protection: hardware features protect against inadvertent writes to the at28c256 in the follow- ing ways: (a) v cc sense - if v cc is below 3.8v (typical) the write function is inhibited; (b) v cc power-on delay - once v cc has reached 3.8v the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of oe low, ce high or we high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typi- cal) on the we or ce inputs will not initiate a write cycle. software data protection: a software controlled data protection feature has been implemented on the at28c256. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the at28c256 is shipped from atmel with sdp disabled. sdp is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to software data protection algorithm). after writing the 3-byte command sequence and after t wc the entire at28c256 will be pro- tected against inadvertent write operations. it should be noted, that once protected the host may still perform a byte or page write to the at28c256. this is done by pre- ceding the data to be written by the same 3-byte command sequence used to enable sdp. once set, sdp will remain active unless the disable com- mand sequence is issued. power transitions do not dis- able sdp and sdp will protect the at28c256 during power-up and power-down conditions. all command se- quences must conform to the page write timing specifica- tions. the data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , read operations will effectively be polling operations. at28c256 2-219
symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1v com., ind. 200 m a mil. 300 m a i sb2 v cc standby current ttl ce = 2.0v to v cc + 1v 3 ma i cc v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma .45 v v oh output high voltage i oh = -400 m a 2.4 v dc characteristics at28c256-15 at28c256-20 at28c256-25 at28c256-35 operating temperature (case) com. 0c - 70c 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c -40c - 85c mil. -55c - 125c -55c - 125c -55c - 125c -55c - 125c v cc power supply 5v 10% 5v 10% 5v 10% 5v 10% dc and ac operating range mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z 3. v h = 12.0v 0.5v. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. operating modes device identification: an extra 64-bytes of e 2 prom memory are available to the user for device identification. by raising a9 to 12v 0.5v and using ad- dress locations 7fc0h to 7fffh the additional bytes may be written to or read from in the same manner as the regu- lar memory array. optional chip erase mode: the entire device can be erased using a 6-byte software code. please see soft- ware chip erase application note for details. device operation (continued) 2-220 at28c256
at28c256-15 at28c256-20 at28c256-25 at28c256-35 symbol parameter min max min max min max min max units t acc address to output delay 150 200 250 350 ns t ce (1) ce to output delay 150 200 250 350 ns t oe (2) oe to output delay 0 70 0 80 0 100 0 100 ns t df (3, 4) ce or oe to output float 0 50 0 55 0 60 0 70 ns t oh output hold from oe, ce or address, whichever occurred first 0000 ns ac read characteristics notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 5ns input test waveforms and measurement level output test load typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v pin capacitance (f = 1 mhz, t = 25c) (1) note: 1. this parameter is characterized and is not 100% tested. at28c256 2-221
symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 100 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns t dv time to data valid nr (1) ac write characteristics note: 1. nr = no restriction ac write waveforms we controlled ce controlled 2-222 at28c256
symbol parameter min max units t wc write cycle time at28c256 10 ms at28c256f 3.0 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 m s t wph write pulse width high 50 ns page mode characteristics chip erase waveforms t s = t h = 5 m sec (min.) t w = 10 msec (min.) v h = 12.0v 0.5v page mode write waveforms (1, 2) notes: 1. a6 through a14 must specify the same page address during each high to low transition of we (or ce). 2. oe must be high only when we and ce are both low. at28c256 2-223
software protected write cycle waveforms (1, 2) notes: 1. a6 through a14 must specify the same page address during each high to low transition of we (or ce) after the software code has been entered. 2. oe must be high only when we and ce are both low. load last byte to last address load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes for software program code: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64-bytes of data are loaded. enter data protect state writes enabled (2) software data protection enable algorithm (1) load data xx to any address (4) load last byte to last address load data 55 to address 2aaa load data aa to address 5555 load data 80 to address 5555 load data 55 to address 2aaa load data aa to address 5555 load data 20 to address 5555 exit data protect state (3) software data protection disable algorithm (1) load data xx to any address (4) 2-224 at28c256
symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns toggle bit characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 0 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. toggle bit waveforms (1, 2, 3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling waveforms at28c256 2-225
2-226 at28c256
(continued) t acc (ns) i cc (ma) ordering code package operation range active standby 150 50 0.2 at28c256(e,f)-15jc 32j commercial at28c256(e,f)-15pc 28p6 (0 c to 70 c) at28c256(e,f)-15sc 28s at28c256(e,f)-15tc 28t at28c256(e,f)-15ji 32j industrial at28c256(e,f)-15pi 28p6 (-40 c to 85 c) at28c256(e,f)-15si 28s at28c256(e,f)-15ti 28t 50 0.3 at28c256(e,f)-15dm/883 28d6 military/883c at28c256(e,f)-15fm/883 28f class b, fully compliant at28c256(e,f)-15lm/883 32l (-55 c to 125 c) at28c256(e,f)-15um/883 28u 200 50 0.2 at28c256(e,f)-20jc 32j commercial at28c256(e,f)-20pc 28p6 (0 c to 70 c) at28c256(e,f)-20sc 28s at28c256(e,f)-20tc 28t at28c256(e,f)-20ji 32j industrial at28c256(e,f)-20pi 28p6 (-40 c to 85 c) at28c256(e,f)-20si 28s at28c256(e,f)-20ti 28t 50 0.3 at28c256(e,f)-20dm/883 28d6 military/883c at28c256(e,f)-20fm/883 28f class b, fully compliant at28c256(e,f)-20lm/883 32l (-55 c to 125 c) at28c256(e,f)-20um/883 28u 250 50 0.2 at28c256(e,f)-25jc 32j commercial at28c256(e,f)-25pc 28p6 (0 c to 70 c) at28c256-w die at28c256(e,f)-25ji 32j industrial at28c256(e,f)-25pi 28p6 (-40 c to 85 c) 50 0.3 at28c256(e,f)-25dm/883 28d6 military/883c at28c256(e,f)-25fm/883 28f class b, fully compliant at28c256(e,f)-25lm/883 32l (-55 c to 125 c) at28c256(e,f)-25um/883 28u at28c256(e,f)-35um/883 28u 50 0.2 at28c256-w die commercial (0 c to 70 c) ordering information (2) at28c256 2-227
(continued) t acc (ns) i cc (ma) ordering code package operation range active standby 150 (3) 50 0.35 5962-88525 16 ux 28u military/883c 5962-88525 16 xx 28d6 class b, fully compliant 5962-88525 16 yx 32l (-55 c to 125 c) 5962-88525 16 zx 28f 5962-88525 15 ux 28u military/883c 5962-88525 15 xx 28d6 class b, fully compliant 5962-88525 15 yx 32l (-55 c to 125 c) 5962-88525 15 zx 28f 5962-88525 14 ux 28u military/883c 5962-88525 14 xx 28d6 class b, fully compliant 5962-88525 14 yx 32l (-55 c to 125 c) 5962-88525 14 zx 28f 50 0.35 5962-88525 08 ux 28u military/883c 5962-88525 08 xx 28d6 class b, fully compliant 5962-88525 08 yx 32l (-55 c to 125 c) 5962-88525 08 zx 28f 5962-88525 07 ux 28u military/883c 5962-88525 07 xx 28d6 class b, fully compliant 5962-88525 07 yx 32l (-55 c to 125 c) 5962-88525 07 zx 28f 5962-88525 06 ux 28u military/883c 5962-88525 06 xx 28d6 class b, fully compliant 5962-88525 06 yx 32l (-55 c to 125 c) 5962-88525 06 zx 28f 200 (3) 50 0.35 5962-88525 12 ux 28u military/883c 5962-88525 12 xx 28d6 class b, fully compliant 5962-88525 12 yx 32l (-55 c to 125 c) 5962-88525 12 zx 28f 50 0.35 5962-88525 04 ux 28u military/883c 5962-88525 04 xx 28d6 class b, fully compliant 5962-88525 04 yx 32l (-55 c to 125 c) 5962-88525 04 zx 28f 250 (3) 50 0.35 5962-88525 13 ux 28u military/883c 5962-88525 13 xx 28d6 class b, fully compliant 5962-88525 13 yx 32l (-55 c to 125 c) 5962-88525 13 zx 28f 5962-88525 11 ux 28u military/883c 5962-88525 11 xx 28d6 class b, fully compliant 5962-88525 11 yx 32l (-55 c to 125 c) 5962-88525 11 zx 28f ordering information (continued) 2-228 at28c256
the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28c256 15 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256e 15 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256f 15 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256 20 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256e 20 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256f 20 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256 25 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256e 25 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256f 25 jc, ji, pc, pi, sc, si, tc, ti, dm/883, fm/883, lm/883, um/883 at28c256 - w valid part numbers t acc (ns) i cc (ma) ordering code package operation range active standby 250 50 0.35 5962-88525 05 ux 28u military/883c 5962-88525 05 xx 28d6 class b, fully compliant 5962-88525 05 yx 32l (-55 c to 125 c) 5962-88525 05 zx 28f 5962-88525 03 ux 28u military/883c 5962-88525 03 xx 28d6 class b, fully compliant 5962-88525 03 yx 32l (-55 c to 125 c) 5962-88525 03 zx 28f 300 50 0.35 5962-88525 10 ux 28u military/883c 5962-88525 10 xx 28d6 class b, fully compliant 5962-88525 10 yx 32l (-55 c to 125 c) 5962-88525 10 zx 28f 50 0.35 5962-88525 02 ux 28u military/883c 5962-88525 02 xx 28d6 class b, fully compliant 5962-88525 02 yx 32l (-55 c to 125 c) 5962-88525 02 zx 28f 350 50 0.35 5962-88525 09 ux 28u military/883c 5962-88525 09 xx 28d6 class b, fully compliant 5962-88525 09 yx 32l (-55 c to 125 c) 5962-88525 09 zx 28f 50 0.35 5962-88525 01 ux 28u military/883c 5962-88525 01 xx 28d6 class b, fully compliant 5962-88525 01 yx 32l (-55 c to 125 c) 5962-88525 01 zx 28f notes: 1. electrical specifications for these speeds are defined by standard microcircuit drawing 5962-88525. 2. see valid part number table below. 3. smd specifies software data protection feature for device type, although atmel product supplied to every device type in the smd is 100% tested for this feature. ordering information (continued) at28c256 2-229
package type 28d6 28 lead, 0.600" wide, non-windowed, ceramic dual inline package (cerdip) 28f 28 lead, non-windowed, ceramic bottom-brazed flat package (flatpack) 32j 32 lead, plastic j-leaded chip carrier (plcc) 32l 32 pad, non-windowed, ceramic leadless chip carrier (lcc) 28p6 28 lead, 0.600" wide, plastic dual inline package (pdip) 28s 28 lead, 0.300" wide, plastic gull wing small outline (soic) 28t 28 lead, plastic thin small outline package (tsop) 28u 28 pin, ceramic pin grid array (pga) w die options blank standard device: endurance = 10k write cycles; write time = 10 ms e high endurance option: endurance = 100k write cycles f fast write option: write time = 3 ms 2-230 at28c256

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